The present invention relates to the field of programmable devices, and the systems and methods for programming the same. Programmable devices, such as FPGAs, typically includes thousands of programmable logic cells that use combinations of logic gates and/or look-up tables to perform a logic operation. Programmable devices also include a number of functional blocks having specialized logic devices adapted to specific logic operations, such as adders, multiply and accumulate circuits, phase-locked loops, and one or more memory units. The logic cells and functional blocks are interconnected with a configurable switching circuit. The configurable switching circuit selectively routes connections between the logic cells and functional blocks. By configuring the combination of logic cells, functional blocks, and the switching circuit, a programmable device can be adapted to perform virtually any type of information processing function.
The configuration of the logic cells, functional blocks, switching circuit, and other components of the programmable device is referred to as configuration data. Configuration data can be stored in volatile or non-volatile memory on the programmable device. Additionally, configuration data can be provided and temporarily or permanently loaded into the programmable device during its manufacturing. Users can specify a user design and generate corresponding configuration data using compilation software tools. The user-created configuration data can be temporarily or permanently loaded into one or more programmable devices to implement the user design. If the user design is changed, updated configuration data can be loaded into the programmable device to implement the changed user design.
Typically, the memory units in programmable devices are designed with timing margins sufficiently large so that despite manufacturing variations and operating conditions, most programmable devices will operate correctly. Although this ensures that the programmable devices are very reliable, excessively large timing margins can result in memory units operating more slowly than necessary. For user designs requiring frequent memory accesses, the speed of the memory units is often a critical limiting factor.
It is therefore desirable for a programmable device to include memory access parameters that can be adjusted after the device is manufactured to maximize memory unit performance. It is desirable for the manufacturer to be able to set memory access parameters of the programmable device after manufacturing and for programmable device users to be able to set memory access parameters of the programmable device to meet the requirements of specific user designs. It is further desirable for the programmable device to implement adjustable memory access parameters with minimal additional overhead.